The superior error correcting performance of turbo codes is associated with the suitable interleaver design. The primary function of the interleaver is to improve the distance properties of the concatenated coding schemes and to disperse the sequence of bits in a bit stream so as to minimize the effect of burst errors introduced in the transmission. The key focus of the proposed work is to design an architecture with minimal hardware complexity and maximum reusable interleaver that can support two standards 3GPP WCDMA and 3GPP LTE. The proposed interleaver/ deinterleaver architecture receives an input data stream of any size established by the 3GPP standard and delivers the interleaved or deinterleaved stream depending on the user requirements. Various optimization techniques and novel VLSI architectures are utilized to achieve the proposed hardware interleaver address generation architecture. By introducing the algorithmic level transformations and hardware reuse methodology low complexity reconfigurable architecture is designed. The frequency of operation of the proposed interleaver is 122.46 MHz. © 2005 - 2014 JATIT & LLS. All rights reserved. © 2014 Elsevier B.V., All rights reserved.