Sivachandra Mahalingam, B. (57192872831) and Ganesh, R. (56702290100) and Parthasarathy, B. (56702568400) and Dhinesh, Meripo (59410748500) (2015) Embedded shift invert transition coding for parallel links.
Full text not available from this repository.Abstract
Power dissipation in a chip mostly depends only on switching activity in a chip (high to low vice versa).Various gating and Encoding schemes are introduced to reduce the unnecessary switching activity of a chip during serial data transmission in a network. But the Encoding methods results in increased bit size and reduces only 15% of the power dissipation (loss). This paper proposed to reduce the switching transitions in a wider Bus, Embedded Shift Invert Coding technique is designed and simulated and its performance is compared with the existing Bus Encoding Techniques. The proposed Embedded Shift Invert Coding technique is first designed and simulated by partitioning the Bus data into two equal width data partitions and applying conventional Shift Invert Coding technique to each of the data partitions. The analysis and simulation results indicate that the Proposed Coding scheme produces a low bit transition for different kinds of data patterns (INV, Left Shift, Right Shift and Normal). © 2015 Elsevier B.V., All rights reserved.
| Item Type: | Article |
|---|---|
| Subjects: | |
| Divisions: | Engineering and Technology > Aarupadai Veedu Institute of Technology, Chennai > Electronics & Communication Engineering |
| Depositing User: | Unnamed user with email techsupport@mosys.org |
| Last Modified: | 11 Dec 2025 06:09 |
| URI: | https://vmuir.mosys.org/id/eprint/4926 |
