Cellular automata (CA) have already established its novelty for bits and bytes error correcting codes (ECC). The current work identifies the weakness and limitation of existing CA-based byte ECC and proposes an improved CA-based double byte ECC which overcomes the identified weakness. The code proposes an idea for multi byte error correction. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed–Solomon (RS) Codes. Also CA-based scheme can easily be extended for correcting more than two byte errors.CA based system can provide simple, regular, modular, and cascadable structure with local interconnection for reliable and high speed operation of the circuit. The system we are implementing have a better scope that it can be used for the error correction purpose in low power applications and as well the computational time taken for the correction of errors is comparatively less than the existing Reed Solomon technique. © 2017 Elsevier B.V., All rights reserved.