The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation

Dimensions

George, Tony Gladvin and Malmurugan, N. (2007) The Architecture of Fast H.264 CAVLC Decoder and its FPGA Implementation. In: Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kaohsiung, Taiwan.

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Abstract

Fast real-time CAVLC decoder (CAVLD) architecture implemented in FPGA. Pipelining between submodules and multi sub-symbol decoding enables 30fps at 1080p, 200 Mbps with 74.25 MHz clock. ALU count: 3266; critical path 10.5 ns. © 2012 Elsevier B.V., All rights reserved.

Item Type: Conference or Workshop Item (Paper)
Subjects:
Divisions: Medicine > Vinayaka Mission's Kirupananda Variyar Medical College and Hospital, Salem
Depositing User: Unnamed user with email techsupport@mosys.org
Last Modified: 10 Dec 2025 07:12
URI: https://vmuir.mosys.org/id/eprint/4453

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