Conference or Workshop Item #4403

Urolagin, Siddhaling and Prema, K.V. and Reddy, N.V. Subba (2007) UNSPECIFIED In: International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007), Sivakasi, Tamil Nadu, India.

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Abstract

Fast real-time CAVLC decoder (CAVLD) architecture implemented in FPGA. Utilizes pipelining between sub-modules and multi-syntax decoding. Integrated with H264 decoder, achieves 30fps for 1080p at 200 Mbps bit rate with 74.25 MHz clock. Critical path within 10.5 ns. © 2007 IEEE. © 2008 Elsevier B.V., All rights reserved.

Item Type: Conference or Workshop Item (Paper)
Subjects:
Divisions: Medicine > Vinayaka Mission's Kirupananda Variyar Medical College and Hospital, Salem
Depositing User: Unnamed user with email techsupport@mosys.org
Last Modified: 10 Dec 2025 07:08
URI: https://vmuir.mosys.org/id/eprint/4403

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