This article presents an efficient multiplication and accumulation (MAC) approaches called “distributed arithmetic (DA) based MAC” and “reconfigurable implementation-based MAC” for alleviating the hardware performances of digital filters. Both reconfigurable implementation and DA-based techniques are combined in this paper at the first time with the help of suitable accumulation structure called “modified carry-save adder (MCSA)” and parallel reconfigurable structure called “dynamically reconfigurable architecture (DRA). Traditionally, DA-based FIR filter implementations require large size of look-up table (LUT) for storing the filter coefficient values. The most disadvantage of DA-based FIR filter implementation is the absence of configurability. Hence, traditional DA-based FIR filter is not suited to wider range of applications. In order to reduce the problem, reconfigurable technique is introduced in MAC unit of DA-based FIR filter implementation. To reduce the complexity form of partial product generation, Reduced Wallace Tree Generation (RWTG) is used along with MAC unit of reconfigurable DA-based FIR filter implementation. In the final stage of RWTG, efficient adder structures are essential to add “n” bit binary data. To meet this requirement, MCSA-based adder is used in the final stage of RWTG. Finally, dynamic or distributed reconfigurable partial product generation (DRRPG) is introduced for producing parallel execution of PPG. Proposed design is estimated by using ALTERA field programmable gate array (FPGA) board by using Quartus II Web Edition tool. The performances of proposed design are validated after implementing in ALTERA FPGA design tool. © 2021 Elsevier B.V., All rights reserved.