Technologies involved in CMOS are reaching the nano processing realm, resulting in scaling challenges for complementary MoSFETs with short channel lengths. Process variations influence design performance and device parameters. FinFET provides better channel control, but lower performance affects 6T Static Random Access Memory (SRAM) circuit function. The bit line loading effect is reduced, improving SRAM performance. Conventional 6T SRAM suffers from conditional stability degradation, low power disturbance, and output voltage issues, affecting read operations. This paper proposes an 8T SRAM cell design to improve stability. Simulation compares the performance of FinFET-based 6T, 8T, and 10T SRAM cells using MicroWind. © 2022 Elsevier B.V., All rights reserved.