At nanometric scales, imprecise computing provides an appealing model for digital processing. Many algorithms decompose multiplication into independent units for parallel processing. This paper focuses on designing 4-2 compressors for use in a multiplier. The proposed design reduces area complexity compared to existing concepts. In the Dadda multiplier, approximation compressors are studied. Simulation and synthesis results show reduced area. ISE simulator is used for functionality checks, and synthesis is carried out using XILINX ISE 14.5 with VERILOG HDL coding. © 2022 Elsevier B.V., All rights reserved.